This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
Hardware Description Languages for FPGA Design
科罗拉多大学波德分校課程信息
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中級
完成時間大約為36 小時
英語（English）
字幕：英語（English）
您將獲得的技能
Writing Code in VerilogSimulating FPGA DesignsDesigning FPGA LogicDesigning Test BenchesWriting code in VHDL
可分享的證書
完成後獲得證書
100% 在線
立即開始，按照自己的計劃學習。
可靈活調整截止日期
根據您的日程表重置截止日期。
中級
完成時間大約為36 小時
英語（English）
字幕：英語（English）
提供方
科罗拉多大学波德分校
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教學大綱 - 您將從這門課程中學到什麼
完成時間為 8 小時
Basics of VHDL
This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.
完成時間為 8 小時
10 個視頻 （總計 48 分鐘）, 2 個閱讀材料, 6 個測驗
10 個視頻
Why Learn VHDL?1分鐘
FPGA Design Flow3分鐘
Intro to VHDL: Finite State Machine3分鐘
How to speak VHDL, first phrases6分鐘
VHDL Assignments, Operators, Types3分鐘
VHDL Rules and Syntax, Interface Ports3分鐘
VHDL in ModelSim: Download and Install3分鐘
VHDL in ModelSim: Adding to your Toolkit6分鐘
Submitting VHDL Programming Assignments11分鐘
2 個閱讀材料
Misson 2-001: Week 1 Readings2小時
Files for Week 1 Programming Assignments10分鐘
2 個練習
VHDL Find the Code Errors30分鐘
Module 1 Quiz30分鐘
完成時間為 12 小時
VHDL Logic Design Techniques
In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.
完成時間為 12 小時
10 個視頻 （總計 52 分鐘）, 2 個閱讀材料, 6 個測驗
10 個視頻
Combinatorial Circuits4分鐘
Synchronous Logic: Latches and Flip Flops4分鐘
Synchronous Logic: Counters and Registers6分鐘
Buses and Tristate Buffers3分鐘
Modular Designs: Components, Generate and Loops in VHDL3分鐘
Test Benches in VHDL: Combinatorial8分鐘
Test Benches in VHDL: Synchronous5分鐘
Memory in VHDL7分鐘
Finite State Machines in VHDL8分鐘
2 個閱讀材料
Week 2 Readings2小時
Files for Week 2 Programming Assignments10分鐘
1 個練習
Module 2 Quiz30分鐘
完成時間為 7 小時
Basics of Verilog
This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.
完成時間為 7 小時
9 個視頻 （總計 92 分鐘）, 2 個閱讀材料, 6 個測驗
9 個視頻
Your First Verilog phrase11分鐘
Verilog Rules and Syntax; Keywords and Identifiers; Sigasi/Quartus editing12分鐘
Verilog Statements and Operators16分鐘
Verilog Modules, Port Modes and Data Types10分鐘
Verilog Structure10分鐘
Testing with ModelSim5分鐘
Verilog Evaluation11分鐘
Submitting Verilog Programming Assignments10分鐘
2 個閱讀材料
Week 3 Readings1 小時 10 分
Files for Week 3 Programming Assignments10分鐘
2 個練習
Verilog Find the Errors20分鐘
Module 3 Quiz30分鐘
完成時間為 10 小時
Verilog and System Verilog Design Techniques
In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.
完成時間為 10 小時
10 個視頻 （總計 48 分鐘）, 2 個閱讀材料, 6 個測驗
10 個視頻
Combinatorial Circuits5分鐘
Synchronous Logic: Latches and Flip Flops3分鐘
Synchronous Logic: Counters and Registers5分鐘
Buses and Tristate Buffers3分鐘
Modular Design in Verilog3分鐘
Testbenches in Verilog7分鐘
Testbenches in Verilog II2分鐘
Memory with Verilog4分鐘
Verilog Finite State Machines7分鐘
2 個閱讀材料
Week 4 Readings15分鐘
Files for Week 4 Programming Assignments10分鐘
1 個練習
Module 4 Quiz30分鐘
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