This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
FPGA Design for Embedded Systems 專項課程科罗拉多大学波德分校課程信息
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第 2 門課程（共 4 門）
中級
完成時間大約為36 小時
英語（English）
字幕：阿拉伯語（Arabic）, 法語（French）, （歐洲人講的）葡萄牙語, 意大利語, 越南語, 德語（German）, 俄語（Russian）, 英語（English）, 西班牙語（Spanish）
您將獲得的技能
- Writing Code in Verilog
- Simulating FPGA Designs
- Designing FPGA Logic
- Designing Test Benches
- Writing code in VHDL
可靈活調整截止日期
根據您的日程表重置截止日期。
可分享的證書
完成後獲得證書
100% 在線
立即開始，按照自己的計劃學習。
第 2 門課程（共 4 門）
中級
完成時間大約為36 小時
英語（English）
字幕：阿拉伯語（Arabic）, 法語（French）, （歐洲人講的）葡萄牙語, 意大利語, 越南語, 德語（German）, 俄語（Russian）, 英語（English）, 西班牙語（Spanish）
提供方
科罗拉多大学波德分校
CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies.
立即開始攻讀碩士學位
此 課程 隸屬於 科罗拉多大学波德分校 提供的 100% 在線 Master of Science in Electrical Engineering。
如果您被錄取參加全部課程，您的課程將計入您的學位學習進程。
授課大綱 - 您將從這門課程中學到什麼
完成時間為 8 小時
Basics of VHDL
This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.
完成時間為 8 小時
10 個視頻 （總計 48 分鐘）, 3 個閱讀材料, 6 個測驗
完成時間為 12 小時
VHDL Logic Design Techniques
In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.
完成時間為 12 小時
10 個視頻 （總計 52 分鐘）, 2 個閱讀材料, 6 個測驗
完成時間為 7 小時
Basics of Verilog
This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.
完成時間為 7 小時
9 個視頻 （總計 92 分鐘）, 2 個閱讀材料, 6 個測驗
完成時間為 10 小時
Verilog and System Verilog Design Techniques
In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.
完成時間為 10 小時
10 個視頻 （總計 48 分鐘）, 2 個閱讀材料, 6 個測驗
審閱
來自HARDWARE DESCRIPTION LANGUAGES FOR FPGA DESIGN的熱門評論
由 MS 提供2020年5月15日
This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.
由 RL 提供2020年5月1日
The Verilog course was very good. However the vhdl course could have been better.Needed a bit more clarity on the assignments.The lectures could have used a bit more explanation.
由 JS 提供2021年6月6日
I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .
由 MB 提供2021年6月23日
Good VHDL intro, Verilog was kind of light, especially the reference material. Free Range VHDL was a great reference. The Verilog section needs something similar.
關於 FPGA Design for Embedded Systems 專項課程
The objective of this course is to acquire proficiency with Field Programmable Gate Arrays (FPGA)s for the purpose of creating prototypes or products for a variety of applications. Although FPGA design can be a complex topic, we will introduce it so that, with a little bit of effort, the basic concepts will be easily learned, while also providing a challenge for the more experienced designer. We will explore complexities, capabilities and trends of Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD). Conception, design, implementation, and debugging skills will be practiced. We will learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP. Projects will involve the latest software and FPGA development tools and hardware platforms to help develop a broad perspective of the capabilities of various Programmable SoC solutions. Topics include:
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