課程信息
4.5
196 個評分
53 個審閱

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立即開始,按照自己的計劃學習。

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中級

完成時間大約為29 小時

建議:6 hours/week...

英語(English)

字幕:英語(English)

您將獲得的技能

Primality TestVerilogDigital DesignStatic Timing Analysis

100% 在線

立即開始,按照自己的計劃學習。

可靈活調整截止日期

根據您的日程表重置截止日期。

中級

完成時間大約為29 小時

建議:6 hours/week...

英語(English)

字幕:英語(English)

教學大綱 - 您將從這門課程中學到什麼

1
完成時間為 5 小時

What's this programmable logic stuff anyway? History and Architecture

What's this programmable logic stuff anyway? In Module 1 you learn about the history and architecture of programmable logic devices including Field Programmable Gate Arrays (FPGAs). You will learn how to describe the difference between an FPGA, a CPLD, an ASSP, and an ASIC, recite the historical development of programmable logic devices; and design logic circuits using LUTs. Examples will include designs of digital adders and multipliers in FPGAs....
9 個視頻 (總計 46 分鐘), 4 個閱讀材料, 2 個測驗
9 個視頻
Course Overview6分鐘
1. Welcome to the world of programmable logic and FPGA design1分鐘
2. A Brief History of Programmable Logic9分鐘
3. CPLD Architecture5分鐘
4. LUTs and FPGA Architecture8分鐘
5. LUTs for Logic Design2分鐘
6. Designing Adders6分鐘
7. Designing Multipliers3分鐘
4 個閱讀材料
About This Course10分鐘
Hardware Requirements10分鐘
Week 1 Suggested Readings20分鐘
Release of Week 2 Files10分鐘
1 個練習
Mission 002: Week 1 Quiz34分鐘
2
完成時間為 5 小時

FPGA Design Tool Flow; An Example Design

In Module 2 you will install and use sophisticated FPGA design tools to create an example design. You will learn the steps in the standard FPGA design flow, how to use Intel Altera’s Quartus Prime Development Suite to create a pipelined multiplier, and how to verify the integrity of the design using the RTL Viewer and by simulation using ModelSim. Using the TimeQuest timing analyzer, you will analyze the timing of your design to achieve timing closure....
11 個視頻 (總計 121 分鐘), 1 個閱讀材料, 3 個測驗
11 個視頻
2. Downloading Quartus Prime2分鐘
3. Installing Quartus Prime2分鐘
4. Introducing Quartus Prime11分鐘
5. Create a design project in Quartus Prime7分鐘
6. Create a design in Quartus Prime13分鐘
7. Compile a Design17分鐘
8. View the RTL16分鐘
9. Timing Analysis with Time Quest I9分鐘
10. Timing Analysis with Time Quest II16分鐘
11. Simulate a design with ModelSim17分鐘
1 個閱讀材料
Week 2 Suggested Readings20分鐘
2 個練習
Mission 003 : Practice Opportunity30分鐘
Mission 005: Week 2 Quiz38分鐘
3
完成時間為 4 小時

FPGA Architectures: SRAM, FLASH, and Anti-fuse

FPGAs are programmable, and the program resides in a memory which determines how the logic and routing in the device is configured. In Module 3 you will learn the pros and cons of FLASH-based, SRAM-based, and Anti-Fuse based FPGAs. A survey of modern FPGA architectures will give you the tools to determine which type of FPGA is the best fit for a design. Architectures will be explored from the basic core logic cell up to consideration of large Intellectual Property (IP) blocks that are available on many FPGAs. ...
8 個視頻 (總計 80 分鐘), 2 個閱讀材料, 1 個測驗
8 個視頻
2. Xilinx CPLD Architecture7分鐘
3. Xilinx Small FPGAs8分鐘
4. Xilinx Large FPGAs11分鐘
5. Altera CPLDs and Small FPGAs8分鐘
6. Altera Large FPGAs9分鐘
7. Microsemi Single-chip FPGA solutions14分鐘
8. Lattice Single-Chip FPGA solutions14分鐘
2 個閱讀材料
Week 3 Suggested Readings20分鐘
Release of Week 4 Files10分鐘
1 個練習
Mission 006: Week 3 Quiz32分鐘
4
完成時間為 7 小時

Programmable logic design using schematic entry design tools

In module 4 you will extend and enhance your design from module 2, completing the design by adding IP blocks, implementing pin assignments and creating a programming file for the FPGA. One outcome will be improved design productivity, by use of design techniques like pipelining, and by the use of system design tools like Qsys, the system design tool in Quartus Prime. You will complete a Qsys system design by creating a NIOS II softcore processor design, which quickly gives you the powerful ability to customize a processor to meet your specific needs. ...
10 個視頻 (總計 180 分鐘), 1 個閱讀材料, 2 個測驗
10 個視頻
2. Advanced Schematic Entry for FPGA Design- Drawing and Hierarchy26分鐘
3. Improving Productivity with IP Blocks25分鐘
4. Improving Timing with Pipelining18分鐘
5. FPGA IO: Getting In and Getting Out8分鐘
6. Pin Assignments: Making them Spot On!20分鐘
7. Programming the FPGA10分鐘
8. Becoming one with Q: Qsys System Design20分鐘
9.a Becoming one with Q Part II: Qsys System Design Finishing Touches25分鐘
9.b Becoming one with Q Part III: Qsys System Design Finishing Touches19分鐘
1 個閱讀材料
Week 4 Suggested Readings10分鐘
1 個練習
Mission 008: Week 4 Quiz32分鐘
4.5
53 個審閱Chevron Right

17%

完成這些課程後已開始新的職業生涯

13%

通過此課程獲得實實在在的工作福利

熱門審閱

創建者 SUSep 18th 2018

Very challenging course with tough assignments and quizes to pass with deadlines but i enjoyed this.\n\nI got practical experience in designing, compiling and analyzing FPGA circuits.

創建者 FCMay 7th 2018

This course will take you from a very basic understanding of FPGA technology to experiencing most facets of the design process. I would like to see more courses on this topic.

講師

Avatar

Timothy Scherr

Senior Instructor and Professor of Engineering Practice
Electrical, Computer, and Energy Engineering

關於 科罗拉多大学波德分校

CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies....

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