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學生對 科罗拉多大学波德分校 提供的 Hardware Description Languages for FPGA Design 的評價和反饋

4.2
86 個評分
36 條評論

課程概述

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....

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VV

Jan 16, 2020

Great experience. Nice learning opportunity. However, please include assignments which are little more diverse and difficult.

SV

May 06, 2020

Good description and Way of explaining.\n\nForums helping out more.\n\nThankyou.

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1 - Hardware Description Languages for FPGA Design 的 25 個評論(共 37 個)

創建者 Michael J M

Feb 08, 2020

This course is confusing and not laid out in a way that is conducive to learning. I would be surprised to know what learning pedagogues the instructors tried to employ. This unfortunately is par for the course from my experience in the colorado university Electrical Engineering department. It is a classic case of "Im an engineer, being in my presence will impart knowledge on you. I don't have a lesson plan or even know what the scientific process of education entails"

This is a teach yourself course with numerous pages of reading but only one of the three books is provided.

In 5 minutes I found online resources for free with step by step examples, vhdl example code, pspice pin outs and testbenches to verify. FOR FREE!!!!!!!

luckily I am not seeking a piece of paper from CU BOULDER. I am seeking knowledge so I am going else where.

創建者 Erik L

Jan 08, 2020

I wish I could give a higher rating, because it is an interesting course. But there are multiple issues with the content, presentation and assignments. I was assured by Coursera that the issues would be addressed by the course providers, but this has not happened.

創建者 Ilan C

Dec 21, 2019

Too simple, no real practice; vhdl and verilog assignments are exactly the same

創建者 Benjamin P A

Jan 28, 2020

So far this course isn't what I expected, very poor explained programming assignments. I'm currently at week 2 and the FIFO assignment and it is not explained very good.

創建者 Shashank V M

Dec 25, 2019

The course was practical and interesting.

創建者 David T

Dec 28, 2019

Though some exercises are not well defined. It was fun to search and debug in the tools. It is one way to learn the great field of FPGA programming. Up to RiscV ...

創建者 Ashish S T

Jan 08, 2020

The content is taught well and the material is helpful to prepare for more intricate circuit designs. I am very satisfied with the guidance through both languages - VHDL and Verilog.

However, there is little guidance for the assignments, many of which are open for interpretation. Unfortunately, this leads to extrapolating the proper instructions through trial and error while investigating simulation results. The course needs to improve clarity for homework assignments.

創建者 Joseph G

Jan 23, 2020

There are a lot of unfixed issues with this course and the instructors are AWOL.

創建者 Miron I

Jan 06, 2020

I am giving 5 stars despite many complaints regarding the missing pieces that hampered our progress. But it was very challenging, and I am still not sure if the so called "errors on Coursera platform" weren't actually purposely introduced by both professor in order to stimulate our neurons in the pursuit of solutions. I am looking forward for the next in series.

創建者 Prakhar C

May 22, 2020

This is really good course for beginners . One aspiring to learn something about verilog and vhdl programming languages could definitely go for this.The assignments and the quizzes are extremely well structured so that the aspirant could gain maximum out of it.

創建者 vasudevan

Jan 16, 2020

Great experience. Nice learning opportunity. However, please include assignments which are little more diverse and difficult.

創建者 silpa k v

May 06, 2020

Good description and Way of explaining.

Forums helping out more.

Thankyou.

創建者 Ranjan Y

Apr 18, 2020

The course is best for beginners and very useful to practice the basics.

創建者 Waseem A

Mar 22, 2020

This course really great and have a lot of fun to learn FPGA Designs.

創建者 Phanindra D

Mar 18, 2020

Great course with in-depth explanations of HDL with Verilog and VHDL

創建者 kasani J g

May 05, 2020

it is really fun to learn this course you will really enjoy it,

創建者 Himanshu G

Mar 29, 2020

A Nice Course which required more hardwork

創建者 Soorya K K

May 08, 2020

Assignment programs are very challenging.

創建者 Ehtesham A K

May 19, 2020

Excellent Course for FPGA learners.

創建者 Lalit B

Mar 04, 2020

feeling satisfactory after successfully completing the course. the instructors were the expert of the topic and explained very well. some of the programming assignments require more clarifications and learning which i found missing in the videos. videos are not enough to complete those assignments.

i am very happy to have this certification and would love to be the part of more learning by the coursera.

創建者 pedram k

Apr 21, 2020

A good combination of introduction to VHDL and Verilog. Cover essential topics for design and test implementation. There are rooms to improvement regarding the assignments description. Also, having the test benches encrypted is fine, but better to make it open source for students once they have get enough grades for that specific problem.

創建者 SHIKHAR S

May 15, 2020

This course provides insights into the world of hardware design. The assignments provided were quite challenging and diverse. The Testbench files were provided on which the code had to be tested and simulation had to be done on ModelSim, provided by MentorGraphics.It was quite an interesting course.

創建者 KUNAL M

May 17, 2020

Good for beginners.Though the instructors can improve upon how they present the concepts by incorporating few complex examples on both Verilog and VHDL.The assignments questions need to be different for both the languages.

創建者 Timothy

May 01, 2020

I did love how explanations were made and especially the flexibility in the submission of quizzes and assignment. My understanding of VHDL and Verilog have been made batter. The instructors are top notch.

創建者 MANISH K S

May 16, 2020

This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.