Chevron Left
返回到 FPGA Softcore Processors and IP Acquisition

學生對 科罗拉多大学波德分校 提供的 FPGA Softcore Processors and IP Acquisition 的評價和反饋

4.1
43 個評分
12 條評論

課程概述

This course will introduce you to all aspects of development of Soft Processors and Intellectual Property (IP) in FPGA design. You will learn the extent of Soft Processor types and capabilities, how to make your own Soft Processor in and FPGA, including how to design the hardware and the software for a Soft Processor. You will learn how to add IP blocks and custom instructions to your Soft Processor. After the Soft Processor is made, you learn how to verify the design using simulation and an internal logic analyzer. Once complete you will know how to create and use Soft Processors and IP, a very useful skill. This course consists of 4 modules, approximately 1 per week for 4 weeks. Each module will include an hour or two of video lectures, reading assignments, discussion prompts, and an end of module assessment....

熱門審閱

BT
2021年6月11日

Must-take Course for Hardware Engineeer. This course provides new concept about NIOS II 32-bit RISC Architecture and How HDL Simulation work

OS
2020年12月8日

I feel I did another small step towards mastering designing with fpga. Thank you!

篩選依據:

1 - FPGA Softcore Processors and IP Acquisition 的 12 個評論(共 12 個)

創建者 Claudio C

2021年8月2日

In t​his course they do not teach you how to create a soft processor, they simply enumerate some of the existing soft processors and other IPs from major FPGA vendors. Then, they show you how to instantiate and configure a system using the Altera's NIOS-II soft processor and enumerate some of the miracles of the eclipse plugin system not knowing exactly what eclipse is.

There is also a very brief introduction to ModelSim for simulation and verification, which the only useful part of this course, and a less than brief introduction to Altera's SignalTap logic analyzer.

As with the rest of the courses of this "specialization", it is 10% useful and 90% useless.

Summarizing: In general, this course is at the level of a badly done free low quality webinar.

Not worth any money, not worth your time.

創建者 Brandon R V

2020年10月11日

Loved the course!

I'm trying everything on my new DE10-Lite.

There's a steep learning curve on the first two weeks, but it all comes together mid week 2.

I had a lot of issues but all of them got solved in the discussion forum.

創建者 Ovidiu S

2020年12月9日

I feel I did another small step towards mastering designing with fpga. Thank you!

創建者 KIMBULOBBE H M T M S S

2020年10月14日

I learned a lot about modelsim that I was really needed.

創建者 Saadiqbal

2021年8月3日

This course brought a great deal of insight in the designing of:

1. NIOS-II processor

2. Integration of pre-existing IP-cores with your design

3. The simulation, debugging and verification of hardware

The core concepts (I have taken from this course) are gemstone and will be guiding star for my future "Embedded system Designing endeavor".

創建者 Bình Đ T

2021年6月12日

Must-take Course for Hardware Engineeer. This course provides new concept about NIOS II 32-bit RISC Architecture and How HDL Simulation work

創建者 Habte G

2021年1月2日

Well prepared lessons(videos). Concise and complete.

創建者 hamza s

2021年10月24日

Very helpful, Thnaks for all

創建者 Harold A M S

2021年9月7日

The course bring good theoric bases to IPCores but leaves short informacion about the Qsys use, memory map and others things that are necesary for system integration.

創建者 Michael W B

2021年8月11日

I was hoping to get more lecture material on writing testbench code.

創建者 Alex G

2021年9月29日

The examples do not compile easily in quartus 20.1. Coding examples need to include more about software and building something that actually works. Course needs to be updated.

創建者 Anthony P

2021年11月18日

A lot of just slide reading and listing, last week of the course is cool because you understand a bit better the simulation