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學生對 科罗拉多大学波德分校 提供的 Hardware Description Languages for FPGA Design 的評價和反饋

469 個評分


This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....




I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .



There are so much use cases that i can apply in my life. thanks so much for giving the psychology know how into the lecture to help us in understanding the root course


126 - Hardware Description Languages for FPGA Design 的 131 個評論(共 131 個)

創建者 Ryan B


The course material can be interesting. However, it's clear that they're looking to get as much paid subscription time from you. They lock off the actual programming assinments behind quizzes which, if you don't get enough right, they delay you for 3 days.

創建者 Rishi D


teacher as well as way of teaching is not good . assignments are great though

創建者 Ethan R


The highlight of this course was the recommended reading materials.

創建者 Surabhi M


not clear.

創建者 saikumar s


There is no technical support

創建者 Muhammet M K