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學生對 科罗拉多大学波德分校 提供的 Hardware Description Languages for FPGA Design 的評價和反饋

4.4
459 個評分
128 條評論

課程概述

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....

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JS

2021年6月6日

I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .

DR

2022年2月20日

There are so much use cases that i can apply in my life. thanks so much for giving the psychology know how into the lecture to help us in understanding the root course

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76 - Hardware Description Languages for FPGA Design 的 100 個評論(共 128 個)

創建者 Vinayakumar R B

2020年5月26日

Very good for beginners

創建者 Ovidiu S

2020年11月17日

High Value Course !

創建者 Rinson V

2020年8月17日

Very good course

創建者 Mucha. S r

2020年8月27日

Awesome course

創建者 Dr. J V S

2020年11月13日

Excellent

創建者 segu v n k

2020年10月29日

very good

創建者 Adil A

2022年4月13日

good one

創建者 Mohsen s

2021年3月27日

thanks

創建者 Penaganti G

2022年1月10日

good

創建者 Sanjana A R

2021年7月11日

創建者 Lalit B

2020年3月4日

feeling satisfactory after successfully completing the course. the instructors were the expert of the topic and explained very well. some of the programming assignments require more clarifications and learning which i found missing in the videos. videos are not enough to complete those assignments.

i am very happy to have this certification and would love to be the part of more learning by the coursera.

創建者 Samer A A

2020年7月7日

The course gives a good overview for the HDL. However, the assignments templates needs to be revised because there were some errors. Also, the requirements sometimes are vague, there is no specific specifications like synchronous/asynchronous signals active high/low clock. But, overall it was good time to revise HDL. I am looking forward to be involved in more advanced courses related to the FPGAs.

創建者 Sangeerth P

2020年6月29日

The course content was worthier and good. But the assignments and the methodology of assessing the assignments were not rigorous. The questions were not clear and elaborate. Once I uploaded a wrong Verilog code but I got 10/10 for that assignment. I don't know how. The course content was really good. But the method of evaluating the assignment could be made better.

創建者 pedram k

2020年4月21日

A good combination of introduction to VHDL and Verilog. Cover essential topics for design and test implementation. There are rooms to improvement regarding the assignments description. Also, having the test benches encrypted is fine, but better to make it open source for students once they have get enough grades for that specific problem.

創建者 Jhoan E L E

2021年10月9日

It is a nice course, I have learned a lot!. However, it can be better if the programming assignments had more comments or hints to debug your codes and complete with the test bench that grade every code. I know Verilog before take this course, but I learned new useful technical and theoretical knowledge.

創建者 SHIKHAR S

2020年5月15日

This course provides insights into the world of hardware design. The assignments provided were quite challenging and diverse. The Testbench files were provided on which the code had to be tested and simulation had to be done on ModelSim, provided by MentorGraphics.It was quite an interesting course.

創建者 Borys I

2020年8月29日

Good training. Could be better. Students should pay attention that most of information they will learn not from video but from books recommended at the end of video. Practical work has abit cryptic task description. what exactly doing particular wire is not clear. U have to google a lot to find out.

創建者 Harold A M S

2021年8月17日

Its a good course that explain the fundamental operators and design methods to construct hardware system units. I only have a trouble with the last design in the week 2 and week 3, and it is that it lacks detail about the requirements of the problem.

創建者 KUNAL M

2020年5月17日

Good for beginners.Though the instructors can improve upon how they present the concepts by incorporating few complex examples on both Verilog and VHDL.The assignments questions need to be different for both the languages.

創建者 Timothy A

2020年4月30日

I did love how explanations were made and especially the flexibility in the submission of quizzes and assignment. My understanding of VHDL and Verilog have been made batter. The instructors are top notch.

創建者 MANISH K S

2020年5月16日

This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.

創建者 Rohit l

2020年5月2日

The Verilog course was very good.

However the vhdl course could have been better.Needed a bit more clarity on the assignments.The lectures could have used a bit more explanation.

創建者 Michael W B

2021年6月23日

Good VHDL intro, Verilog was kind of light, especially the reference material. Free Range VHDL was a great reference. The Verilog section needs something similar.

創建者 harsh

2020年5月15日

The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.

創建者 Rishi J

2020年9月4日

The course is good. It will enhance your vhdl and verilog skills but there are some places where i found insufficient details.