So here in lecture 11.9 were going to complete our exploration of maze routing,
and were actually going to look at a, just a slightly different topic.
but again something based on the core maze routing methods.
So again, over and over, one of the things we've been emphasizing is that one
of the things that's just great about the maze routing idea is that it is so
flexible and so adaptable. All of the routers that we have been
talking about so far in this lecture series are what are called, detailed
routers. And what a detailed router is is a router
that actually embeds a wire in a physical way that could make a physical path.
There's another kind of a routing process and these are called global routers.
A global router does not put the physical wire down in the physical final path.
The Global Router tells you, roughly speaking the wire wants to go, kind of,
sort of, over here. Think of this as a hierarchical
decomposition of routing. Instead of decomposing the chip surface
into a gigantic grid of tiny little cells, each of which can fit one wire.
We decompose the chip surfacing to a coarse grid of cells, each of which could
hold, say, a couple of hundred wires. And on this coarse grid, we route.
What does it mean to have a cost in this coarse grid?
What does it mean to traverse a cell in this coarse grid.
What does it mean to be an obstacle in a course grid that's the size of, you know,
200 wires on this dimension and 200 wires on this dimension.
there's an entire parallel ecosystem of ideas in global routing that lets us
coarsely. And efficiently plan the macroscopic
paths of the 25 or so million nets on a really big ASIC.
In an efficient way, so that when we finally invoke the detailed routing, we
don't actually run the maze router on the full surface of the chip.
We run it in little sort of boxes where we know the net already wants to go.
An the beautiful thing is, it's just another maze router.
It's just another expansion process. It's just another interesting set of cost
functions. An it is really, really the way, big
things get routed. So, let's finish our exploration of
routing for ASICs and the maze routing method in particular, by talking about
global routing. We're going to finish our discussion of
maze routing by kind of popping up a level to sort of talk about the, the, the
big picture problem again. And, as a starting point let's, we're
going to do a little bit of a reality check.
so you know here's, here's just my great big giant chip that I showed at the
beginning of this lecture this is an industrial actually a, a processor chip.
let's say that something like this is maybe one centimeter on the side, 20 to
50 million nets in a modern integrated circuit technology.
The grid as we taught you about the wiring grid, probably has the picture of
the wires which means the centre of one wire to the center of the closest
adjacent wire. Which we can think of, its the size of a
grid cell, maybe about a 100 nanometers. So if you have 1 centimeter, and you have
a 100 nanometer grid, you have 100000 grids on each.
on the X axis and the Y axis. And then if you multiply that by 10
different routing layers, you get about 100 billion grid cells.
So, this is one of the reasons I said we care about how big the grid cells are,
and we'd like to have as few bits as possible.
But, but do w-, we really just do it like this?
And the answer is not, not really. there's some more interesting stuff that
happens. So the first fact just as an aside is
that in, in real industrial ASIC routers we have like ten layers of wiring.
Every other layer of metal wiring has a preferred direction.
So let's say, for example, metals 3, 5, 7 and 9 are vertical Metals 4, 6, 8, and 10
are horizontal and this is how strong this preference is.
Is just a function of the, the router and the preference of the user but I'm just
going to show you an example where it's strictly enforced.
so suppose I've got a chip and I've got a pen on layer three.
as I've shown over here I've got a pin on layer six, how do I route it.
you know, I mean the typical way I'd route something like this is I'd route it
vertically on layer three. And then I'd pop a via in and then I'd go
horizontally on layer four, then I'd pop a via in, and then I'd go vertically on
layer six and I'd pop a via up to. Layer set.
So I'd, vertically on layer five, and I'd pop a via up and I'd drop that connection
in on layer six. And so the idea is that if you need to
bend, use a via. Or, and people will play games with the
bend penalty, you're allowed to bend, but boy very, very little.
and the whole idea is that the wires on these layers look like mostly straight
lines. Right, which makes it much much much
easier to route a lot of things that are just going in straight lines.
It is harder, harder to block stuff. Okay?
And when you need to go around, you go to another layer that is mostly straight
lines. So that is one of the ways you deal with
the complexity. but there is another interesting way,
which is the divide and conquer scheme. So how do you deal with a huge, the huge
scale of chips? The first kind of routing is called
global routing. and global routing is again a grid based,
maze routing, kind of a thing. and so we have a grid on which we run a
certain kind of a maze router. But the thing that's different is that
the grid is not a one wire per cell grid. The grid is now very coarse.
So the grid might be a set of boxes on the surface of the chip that are maybe
200 wires by 200 wires in size. So, the grid is extremely coarse.
And the big idea is that you run the maze router on your wire.
Just through these great big coarse regions.
So I've got a, you know, a little yellow wire here, going from a pin in the upper
left to a pin in the lower right. Now, why am I doing this?