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Small-Dimension Effects - Scaling and New Technologies

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MOS 晶体管

哥伦比亚大学

4.6（126 個評分） | 29K 名學生已註冊

PLEASE NOTE: This version of the course has been formed from an earlier version, which was actively run by the instructor and his teaching assistants. Some of what is mentioned in the video lectures and the accompanying material regarding logistics, book availability and method of grading may no longer be relevant to the present version. Neither the instructor nor the original teaching assistants are running this version of the course. There will be no certificate offered for this course. Learn how MOS transistors work, and how to model them. The understanding provided in this course is essential not only for device modelers, but also for designers of high-performance circuits.

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4.6（126 個評分）

5 stars
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4 stars
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SS

Apr 12, 2017

I come from electrical engineering background. I found the material in the course very insightful and easy to follow.

RS

Jul 18, 2017

Extremely useful and well planned course! Must for every analog circuit designer...

從本節課中

Small-Dimension Effects 2; Modeling for Circuits Simulation

This module we will finish with small dimension effects, and then talk about models for circuit simulation (the circuit designers among you are probably already using such models). We discuss what it takes to make a good model for circuit simulation (among other things: a lot of caution and care, and about 20,000 lines of code!), and how you can spot possible problems with such models. Although models for circuit simulation include capabilities we have not yet discussed, such as charge modeling, we think you know enough about models at this point to be able to follow this general discussion (which is out of sequence – it’s from Chap. 10 in the book, where you can find much more on the subject).

Small-Dimension Effects - Scaling and New Technologies9:48

Modeling for Circuit Simulation – Approaches and Properties of Good Models11:52

Modeling for Circuit Simulation – Model Formulation Considerations6:48

教學方

Yannis Tsividis
Charles Batchelor Professor of Electrical Engineering

腳本

In this video we'll conclude our discussion of small dimension effects.

We will discuss how in the past technologies tried to make smaller and

smaller devices. and we will see that those techniques no

longer work and we will briefly discuss how devices are optimized today.

Let me begin with a very short summary of how technology used to evolve years ago.

Let's say technology had reached, dimensions shown over here.

So this is the minimum channel length, that had been achieved in order to keep

in check, short channel effects. And, what was desired, was, to increase

the speed of devices, which means you want to make the distances between any

two points shorter. And also to increase the number of

transistors per unit area. The way to do that, of course, was to try

to decrease channel length. Make this shorter.

But when you do that, you approach a limit, because the source and drain

depletion regions approach each other. So if you want to decrease the channel

length, you have to make the depth of the depletion regions, smaller.

So you need to decrease the depletion region depth, and at the same time, you

need to make the oxide thinner, so that you maintain control of the gate, on the

channel. Now, to decrease the depletion region

depth, would imply that you have to make The body concentration, larger.

So you have a high doping concentration here, and then the extent of the

depletion region here, is smaller than there.

And at the same time, you decrease the doping thickness.

So basically the new device, is like a, reduction of a photo of the old device.

Everything goes down in proportion so if this device was good enough, and it could

keep the short channel effects in check, this one does too.

Now, of course when you decrease distances, if you keep the voltages the

same, the electric field goes up, and then you have other problems, like hot

electron effects. So, to keep the peak electric fields from

increasing, you would have to decrease voltages.

So power supply voltages kept decreasing. Now, there have been several variations

of the above general scenario that I showed you.

they go by the name of constant field scaling, constant voltage scaling,

quasi-constant voltage scaling, generalized scaling.

And,these actually help produce new generations of devices for a couple of

decades, but now, they have reached their limits.

I would advise you to spend some time reading the corresponding part in the

book because it is instructive. the way these things were done and the

way it is described will give you a general feel for how things move when you

change dimensions. But today, our primary concern is

participation, and in fact, a big Headache in that whole area is the

leakage currents. Let's assume digital operation.

We want to have a large driving current i on in order to charge parasitic

capacitances as fast and have achieved high speed.

And then when a device is off we want to have a very small leakage current high

off to limit participation due to leakage.

Now, unfortunately, the weak inversions slope when you scale dimensions down

doesn't scale. And you have a situation like this.

This is the log of the current, is actually the current on a log axis versus

VGS and we have a current that goes from weak inversion to moderate to strong

inversion. When we apply the maximum possible

voltage on the chip which is VDD with VDD being the power supply voltage.

We get enough current i on to drive our parasitic capacitances fast and achieve

high speed as I said. When we lower VGS to 0, then we want to

have very low leakage current ioff. So the range of voltages you need to

apply to have a satisfactory distance between I on and I off is all of this.

If you now desire to go to a smaller power supply voltage, let's say VDD

prime, then what you're going to find is that i on, at this value, is smaller.

And remember, this is a logarithmic access, so this i prime on, is

significantly smaller than i on, and doesn't give you enough drive .

So you say okay, well if that is the case, why don't I increase the threshold

of the device so that we shift this curve to the left, and then the current here

will increase. For example, why don't I do that.

Now, for the new supply voltage V D T prime, I have as much current as before,

I ON. But, look now what happened.

I off now, is very large. So you cannot afford to do that, because

it gives you a large leakage current, which corresponds to large static power

dissipation. And when you have short channel effects,

things become even worse, because with severe short channel effects, as we have

seen before. The slope in the weakened version region

deteriorates, and gives you an even higher i off.

So, you are really between two conflicting requirements, and it is not

possible to keep decreasing the power supply voltage.

So the typical scaling that used to carry us from generation to generation years

ago is no longer possible and modern device engineering.

Relies on other techniques, which include doping profile engineering.

For example, the halo implants that we have already seen.

New insulator materials like hafnium. New gate materials, metal gates.

Strain engineering which we will see later on to increase mobility and even

new device structures. there are several new device structures.

I will just show you a couple. One is the ultra thin body on SOI.

SOI I remind you stands for silicon on insulator.

And it looks like this. You have a silicone substrate, an oxide

on top of it and you have a very thin body transistor.

This is the source, this is the body and this is the drain.

And with enough gate voltage here you can deplete the entire body.

Now because you don't have a large body here, it, it can be shown you have fewer

effects with leakage. You have no problem with floating bodies

and things like that. And, this is built on a ultra thin SOI

wafer, which is, somewhat more expensive than a normal wafer, but you achieve

reduced short channel effects. You limit the effect to the degree to

which the source and drain can effect what happens to the channel.

Of a more widely advertised process is the Tri-gate process which a variation of

the Fin, FinFET process. It's currently used by Intel's 22

nanometer technology. And in ops doc form it looks like this.

This is the channel in three dimensions and you have a gate that surrounds the

channel on three sides. The source and drain are thicker here in

order to make contact into them. But, the main channel is this one.

Because now, you surround the device on three sides, you keep better control of

the channel, and you reduce short channel effects.

I remind you, when we discussed charge sharing in particular, we talked about

the fact that the gate competes with a source in the drain In keeping control of

the channel. Here, since the gate hugs the channel in

this way, it gives better control on the channel and the corresponding control of

source and drain on the channel is weaker.

So you have reduced short channel effects this way.

There are many variation, several variations of this structure.

In both of these structures, the channel is fully depleted.

So we have seen in this lecture, a short summary of the scaling process, that used

to carry us from generation to generation years ago.

And, a short, a brief summary of how things are done today in order to produce

high performance devices with very small dimensions.

At this point we have finished our small dimension effects lectures.

Starting next time, we will be talking about CAD modelling.

How all of this can be incorporated into CAD models, and what makes CAD models

good or bad.

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