We could define a package that includes several definitions and functions,

a package called for example my_fsm.

It defines the set of internal states. So, a type STATE

is defined equal to, for example, S0, S1, S2, and so on.

In the package, we define the number N of input signals

(I mean, the number of bits necessary to encode the input state),

a number M of output signals (that means

the number of bits that encode the output state),

and we could define in some way, by tables or by algebraic expressions,

the next state function F, and the output function H.

Then, we define an entity MooreFsm

with input ports CLK, RESET and X.

CLK and RESET our bits, and X is an N-bit vector,

and with one output port Y, an M-bit vector.

The architecture includes the declaration of a

signal current_state, whose type STATE has been defined in the package.

A first process next_state, sensitive to RESET and CLOCK is the following:

(it's easy to understand)

if reset is equal to 1, then current_state will be equal to S0

(we assume that S0 is the initial state of the finite state

machine); then, if there is a positive edge of the clock

signal (it is the way VHDL defines this condition)

if there is a positive edge of the clock signal then

the current state is replaced by the function F of the

current state and of the input state. Nothing else.

The output process, sensitive to the current state computes Y,

a function of the current state, using for that function H defined within

the package. In fact, instead of defining F and H within

a separate package, they could also be directly defined within the processes.

Then the next_state process could be based on a "case" statement.

So, here is the next_state process, sensitive

to RESET and CLCK, the same as before:

if reset is equal to 1 then current_state is equal to S0;

else, if there is a positive edge of the clock signal,

then, in the case that current_state is S0

then (here) you will insert a set of instructions that update

the current state of the machine, that is to say, a set of instruction that

execute current_state = F(S0, X).

The same when the current state is S1, S2, and so on.

And the same as regards the output state process, sensitive

to the current state, and then the body of the process

is a "case" statement: when the current state is S0,

we insert here a set of instructions

that execute Y = H(S0).

The same when the current state is S1, and so on.

Let us see an example.

Again, the 3-bit counter.

So, we assume that we have previously defined the type

STATE equal to 0, 1, 2, 3, and so on, up o 7,

that we have declared an input port count_enable,

a bit, and an output port Y, a 3-bit vector.

The next state process is as follows: it's a process sensitive to RESET and

CLK. If reset is equal to 1, next state is 0;