JS
2021年6月6日
I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .
DR
2022年2月20日
There are so much use cases that i can apply in my life. thanks so much for giving the psychology know how into the lecture to help us in understanding the root course
創建者 Aishwarya S
•2020年5月7日
FIFO assignments in both Verilog and VHDL should define purpose of all the internal nets and registers listed in the problem.
創建者 Julio T A
•2021年4月2日
Siento que faltan mas ejemplos y practicas, y en cuanto al apartado de lenguaje Verilog falta explicar aun mas sintaxis
創建者 Raghul R
•2020年6月25日
Teaching methodology requires a lot more improvement. Assignments are challenging and its nice to try.
創建者 KUNAPAREDDY S N
•2020年5月14日
this course is given good idea of Hardware Description Language and i understood the concepts well.
創建者 Muhammad Z Y
•2020年4月7日
Course content is moderate. But also have complexity level higher for a beginner.
創建者 Uzair A
•2020年10月9日
its a very nice course. Its help me a lot to understand the basic of fpga.
創建者 Apoorva S
•2020年5月25日
A very engaging course to do for beginners having fundamentals strong.
創建者 Yuvraj S R
•2020年5月18日
Explanations are not that good for some circuits like memory
創建者 Sourav N
•2020年9月18日
There should have been more examples of problems.
創建者 Mohamed C
•2020年4月30日
a big thank you to all the professiors
創建者 Engels M
•2021年12月3日
Concise, practical and useful
創建者 Prakash K R
•2020年6月24日
It should be more elaborative
創建者 TUMMALAPALLI S V N S
•2020年6月7日
BEST FOR THE BASIC
創建者 J S
•2020年8月5日
good
創建者 Adriel K
•2022年3月16日
The course is OK, but the videos are terrible. The presenters do nothing more than just read the slides as they appear, which are sometimes just a page of code. In the VHDL section, I believe the presenter is seeing the material for the first time. I ended up just turning the audio off and treating the videos as a slide deck, which worked quite well. The assignments were fun.
創建者 Julien T
•2021年12月7日
Interesting course but exercises shall be reworked as sometimes it's not clear what is the expected output so we end up guessing via the testbench. Another issue is that some half backed quizzes prevent you from practicing the exercises until you pass even though practicing is key to understand the concepts...
創建者 Islam E
•2020年5月31日
this course need a person who knows before the basics of both VHDL/Verilog. because i know some basics of VHDL i understood its part but verilog was a little bit hard to me to understand it
創建者 Harsh A
•2020年6月15日
Verilog part is explained very well but VHDL part completely unsatisfied.
創建者 Sachin A
•2020年4月21日
Very introductory. Verilog and VHDL exercises are copied.
創建者 Sakshat R
•2020年5月28日
Innovative teaching, but very poor assignments
創建者 Samuel C
•2020年8月14日
A decent introduction to HDL.
創建者 Pushkar A
•2020年9月30日
Teaching could be better.
創建者 JYOTI S S
•2021年7月11日
good
創建者 Rishi D
•2020年6月12日
teacher as well as way of teaching is not good . assignments are great though
創建者 Ethan R
•2020年4月11日
The highlight of this course was the recommended reading materials.