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學生對 科罗拉多大学波德分校 提供的 Hardware Description Languages for FPGA Design 的評價和反饋

4.4
459 個評分
128 條評論

課程概述

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....

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JS

2021年6月6日

I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .

DR

2022年2月20日

There are so much use cases that i can apply in my life. thanks so much for giving the psychology know how into the lecture to help us in understanding the root course

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26 - Hardware Description Languages for FPGA Design 的 50 個評論(共 128 個)

創建者 GHULAM R

2020年10月17日

Thank you so much Coursera for offering this course and to the teachers who put their efforts to make this course easy to learn. Before joining this course I only had experience on C language and microcontrollers and having completed this course I am able to do basic FPGA coding using VHDL or Verilog. This course also taught how to use ModelSIm software and its simulations. I recommend this course to anyone who want to learn Hardware descriptive language and get started with FPGA. Thank you again.

創建者 Pratham N

2020年5月30日

An overall understanding can be gained after finishing this course, in areas involving Verilog, Digital Systems design using HDL, and a basic idea on how fpga's implement the code developed.

Had a great time learning and i'm very grateful to Univ of Colorado Boulder and Coursera for giving me this beautiful opportunity. And always cheers to Andrew Ng and team! Thank you guys.

創建者 Miron I

2020年1月6日

I am giving 5 stars despite many complaints regarding the missing pieces that hampered our progress. But it was very challenging, and I am still not sure if the so called "errors on Coursera platform" weren't actually purposely introduced by both professor in order to stimulate our neurons in the pursuit of solutions. I am looking forward for the next in series.

創建者 Cosimo M

2020年10月24日

A truly beautiful course. This chapter of digital electronics is truly fascinating and particular. Unfortunately, it is not treated as a topic in my university course. The other interesting thing was the implementation of the two languages on the same exercises. Congratulations and thank you.

創建者 Gabriel G

2020年8月24日

Good introduction to HDL for both, VHDL and Verilog. You need a good basis of digital electronic and some background on coding but not too much as the course is very introductory but giving examples and bottom to top approach. Highly recommended to those that want to start from somewhere.

創建者 Victor G

2020年9月29日

as the first course I have had for HDL it is perfect. The combination of structured lecutre materials, pretty challenging for the beginners problems to solve, good list of reading materials makes this course very comfortable for later use for real taks solving.

創建者 PRAKHAR C

2020年5月22日

This is really good course for beginners . One aspiring to learn something about verilog and vhdl programming languages could definitely go for this.The assignments and the quizzes are extremely well structured so that the aspirant could gain maximum out of it.

創建者 Dmitry K

2021年4月30日

Course opens mind for HDL and allows to select what you like more - VHDL or Verilog. Very useful if you have basic knowledge of FPGA otherwise if you are the beginner in FPGA - start with the first course (a must).

創建者 Erick A M D

2022年2月27日

The way to introduce both programming languages is very natural.

Quizes are a little confusing at first, but they helped me to understand the underlaying concurrent behavior of FPGAs.

創建者 Jogesh S

2021年6月7日

I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .

創建者 Abbe A

2020年12月26日

Excellent content. The exercises could be more detailed though. I learned a lot about Verilog, Modelsim and I practiced my VHDL knowledge.

創建者 Gabriel G C M

2021年8月27日

Excellent course! A broad review of several topics! Great videos and great assignments! I have been loving this specialization!

創建者 Holman H B C

2021年5月8日

Good reading materials. The videos are concise. However, it could improve the code programming assignments to be more explicit.

創建者 Joseph V

2021年2月23日

Professors were top-notch and clearly explained the pros and cons of each of the languages. I hope I could meet them in person.

創建者 Vasudevan M

2020年1月16日

Great experience. Nice learning opportunity. However, please include assignments which are little more diverse and difficult.

創建者 Suhaas N

2020年7月8日

Though the support of this course is quite poor and the forum is really dull, the course in itself is really something!!

創建者 Gregory P

2021年5月1日

Very good course. lectures, assignments and provided reading material provide a solid foundation for writing HDL code.

創建者 Ayush s

2022年1月16日

good course for getting hands on exposure for learning VHDL and verilog in less time, found it very useful.

創建者 Jinendar K

2022年3月28日

bhut sexy course. mujhe nhi krna ab fir bhi enroll nhi kr paa rha .feeling happy and semd at the same time

創建者 Raychel G

2021年10月10日

I've been able to learn pleasantly VHDL and verilog hardware description language I've never experienced.

創建者 19MR12_VENKATESHWARAN K

2020年6月22日

WELL DEFINED EXPLANATION AND VERY GOOD MATERIALS PROVIDED WITH REAL DATA SHEET PROBLEMS TO BE ADDRESSED

創建者 Jesus A R A

2020年8月5日

Nice course but the FIFO wasn't explained clearly in both time but I still completed it with some help

創建者 Akash G

2020年8月31日

amazing experience, great course and handled very easily with the help of two great instructors

創建者 Jakub L

2020年7月8日

Very nice entry level course, teaches the basic concepcts very clearly, overall great.

創建者 hyungok t

2021年2月26日

I think that SystemVerilog Design and Verification contents are more required!