本課程是 FPGA Design for Embedded Systems 專項課程專項課程的一部分

4.8
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14 個評分
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5 條評論

Timothy Scherr

4,296 人已註冊

提供方

隸屬於 Master of Science in Electrical Engineering 學位

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FPGA Design for Embedded Systems 專項課程科罗拉多大学波德分校

課程信息

7,001 次近期查看

This course will give you hands-on FPGA design experience that uses all the concepts and skills you have developed up to now.   You will need to purchase a DE10-Lite development kit.  You will setup and test the MAX10 DE10-Lite board using the FPGA design tool Quartus Prime and the System Builder.
You will:  
Design and test a Binary Coded Decimal Adder. 
Design and test a PWM Circuit, with verification by simulation. 
Design and test an ADC circuit, using Quartus Prime built-in tools to verify your circuit design. 
Create hardware for the NIOS II soft processor, including many interfaces, using Qsys (Platform Designer). Instantiate this design into a top-level DE10-Lite HDL file.
Compile your completed hardware using Quartus Prime.  
Enhance and test a working design, using most aspects of the Quartus Prime Design Flow and the NIOS II Software Build Tools (SBT) for Eclipse.
Create software for the NIOS II soft processor, including many interfaces, using Qsys (Platform Designer) and the SBT.
Compile your completed software using the SBT.
Use Quartus Prime to program both the FPGA hardware configuration and software code in you DE10-Lite development kit.  
Record all your observations in a lab notebook pdf. 
Submit your project files and lab notebook for grading.
This course consists of 4 modules, approximately 1 per week for 4 weeks.   Each module will include an hour or less of video lectures, plus reading assignments, discussion prompts, and project assignment that involves creating hardware and/or software in the FPGA.

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可分享的證書

完成後獲得證書

100% 在線

立即開始，按照自己的計劃學習。

第 4 門課程（共 4 門）

FPGA Design for Embedded Systems 專項課程

中級

You should have a experience in digital design and C programming before taking this course, and also complete the first 3 courses in this series.

完成時間大約為29 小時

英語（English）

字幕：法語（French）, （歐洲人講的）葡萄牙語, 俄語（Russian）, 英語（English）, 西班牙語（Spanish）

您將學到的內容有

Create a working FPGA design using Quartus Prime and run it on an evaluation board
Understand and practice all aspects of FPGA development, including conception, design, implementation, and debugging.
Create in the FPGA a working system on a chip design with Nios II soft processor, RAM and FLASH memory, and several peripherals.
Become familiar with the FGPA development flow, particularly in the case of a SoC with software development flow included.

您將獲得的技能

Softcore Processor Design
Programmable Logic Design

可靈活調整截止日期

根據您的日程表重置截止日期。

可分享的證書

完成後獲得證書

100% 在線

立即開始，按照自己的計劃學習。

第 4 門課程（共 4 門）

FPGA Design for Embedded Systems 專項課程

中級

You should have a experience in digital design and C programming before taking this course, and also complete the first 3 courses in this series.

完成時間大約為29 小時

英語（English）

字幕：法語（French）, （歐洲人講的）葡萄牙語, 俄語（Russian）, 英語（English）, 西班牙語（Spanish）

授課教師

授課教師評分

4.83/5 （6 個評分）

Timothy Scherr

Senior Instructor and Professor of Engineering Practice

Electrical, Computer, and Energy Engineering

75,837 個學生

5 門課程

提供方

科罗拉多大学波德分校

CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies.

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此課程隸屬於科罗拉多大学波德分校提供的 100% 在線 Master of Science in Electrical Engineering。如果您被錄取參加全部課程，您的課程將計入您的學位學習進程。

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授課大綱 - 您將從這門課程中學到什麼

週

週 1

完成時間為 10 小時

Hands on: Altera MAX10 Hardware Setup

In this module you will begin your hands-on exploration of FPGA design by setting up a target board, the DE10-Lite based on the MAX10 Intel Altera FPGA. In this module you will

完成時間為 10 小時

5 個視頻（總計 15 分鐘）, 4 個閱讀材料, 8 個測驗

5 個視頻

FPGA Capstone: Building FPGA Projects Course Introduction2分鐘

Capstone Project: Starting FPGA Design1分鐘

Board Setup and Test1分鐘

Expected Outcomes for Module 15分鐘

Tips for Success3分鐘

4 個閱讀材料

How to Purchase the DE10-Lite Development Kit10分鐘

FPGA Captstone: Building FPGA Projects Assessment Strategy10分鐘

Module 1 Project Guide30分鐘

Lab Notebook Template20分鐘

1 個練習

Module 1 Quiz30分鐘

週

週 2

完成時間為 8 小時

Develop a Mixed Signal System

The goal of this module is to develop a mixed-signal system. You will construct hardware that uses the Analog to Digital Converter (ADC) inputs and Pulse Width Modulate (PWM) outputs to make a voltage measuring instrument. In this module you will

 Create a working design, using most aspects of the Quartus Prime Design Flow.  Design and test a PWM Circuit, with verification by simulation.  Design and test an ADC circuit, using Quartus Prime built-in tools to verify your circuit design.  Record all your observations in a lab notebook pdf.  Submit your project files and lab notebook for grading. Completing this module will help prepare you for the work to be done in the modules that follow.

完成時間為 8 小時

2 個視頻（總計 4 分鐘）, 1 個閱讀材料, 4 個測驗

週

週 3

完成時間為 8 小時

Create a System on a Chip with NIOS II

The goal of this module is to develop the hardware for a System on a Chip (SoC). You will construct hardware that creates a NIOS II soft processor along with several interfaces to devices on the DE10-Lite development kit. In this module you will

 Create a working design, using most aspects of the Quartus Prime Design Flow.  Create hardware for the NIOS II soft processor, including many interfaces, using Qsys (Platform Builder). Instantiate this design into a top-level DE10-Lite HDL file.  Compile your completed hardware using Quartus Prime.  Record all your observations in a lab notebook.  Submit your project files and lab notebook for grading. Completing this module will provide a platform for the work to be done in the module that follows.

完成時間為 8 小時

2 個視頻（總計 5 分鐘）, 1 個閱讀材料, 3 個測驗

週

週 4

完成時間為 5 小時

Software for a System on a Chip

The goal of this module is to develop the software for a System on a Chip (SoC). You will build software for a NIOS II soft processor you built in Module 3, using several interfaces to devices on the DE10-Lite development kit as well. In this module you will

 Enhance and test a working design, using most aspects of the Quartus Prime Design Flow and the NIOS II Software Build Tools (SBT) for Eclipse.  Create software for the NIOS II soft processor, including many interfaces, using Qsys (Platform Builder) and the SBT.  Compile your completed software using the SBT.  Use Quartus Prime to program both the FPGA hardware configuration and software code in you DE10-Lite development kit. You will then test your new embedded system.  Record all your observations in a lab notebook pdf.  Submit your project files and lab notebook for grading. Completing this module will finish your work for this course.

完成時間為 5 小時

2 個視頻（總計 5 分鐘）, 1 個閱讀材料, 3 個測驗

審閱

4.8

5 條評論

5 stars
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4 stars
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3 stars
7.14%

來自FPGA CAPSTONE: BUILDING FPGA PROJECTS的熱門評論

由 CL 提供2022年1月25日

In general a good course structure and content. It lacks support on question and exercises.

由 DK 提供2021年5月28日

Requires knowledge of FPGA design flow (make sure to take 3 courses before this one), great practical tasks that complete the whole specialization.

由 OS 提供2021年1月27日

This specialization has a very good balance between deepness and breadth of transmitted knowledge. Thank you !

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關於 FPGA Design for Embedded Systems 專項課程

The objective of this course is to acquire proficiency with Field Programmable Gate Arrays (FPGA)s for the purpose of creating prototypes or products for a variety of applications. Although FPGA design can be a complex topic, we will introduce it so that, with a little bit of effort, the basic concepts will be easily learned, while also providing a challenge for the more experienced designer. We will explore complexities, capabilities and trends of Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD). Conception, design, implementation, and debugging skills will be practiced. We will learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP. Projects will involve the latest software and FPGA development tools and hardware platforms to help develop a broad perspective of the capabilities of various Programmable SoC solutions. Topics include:

Verilog, VHDL, and RTL design for FPGA and CPLD architectures FPGA development tools flow: specify, synthesize, simulate, compile, program and debug Configurable embedded processors and embedded software Use of soft-core and hard-core processors and OS options FPGA System engineering, software-hardware integration, and testing IP development and incorporating 3rd-party IP The capstone course will give the learner the opportunity to practice and implement the concepts covered by building FPGA systems based on low cost evaluation boards.

常見問題

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讲座和作业的访问权限取决于您的注册类型。如果您以旁听模式参加课程，则可以免费查看大多数课程资料。要访问评分作业并获得证书，您需要在旁听期间或之后购买证书体验。如果看不到旁听选项：
课程可能不提供旁听选项。您可以尝试免费试用，也可以申请助学金。
课程可能会改为提供'完整课程，没有证书'。通过此选项，您可以查看所有课程材料、提交所要求的作业，以及获得最终成绩。这也意味着您将无法购买证书体验。
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您注册课程后，将有权访问专项课程中的所有课程，并且会在完成课程后获得证书。您的电子课程证书将添加到您的成就页中，您可以通过该页打印您的课程证书或将其添加到您的领英档案中。如果您只想阅读和查看课程内容，可以免费旁听课程。
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FPGA Capstone: Building FPGA Projects